7. Constraints Manual

LegUp accepts user-provided constraints that impact the automatically generated hardware. These constraints can be specified using the LegUp IDE and are stored in the Tcl configuration file config.tcl in your project directory. This reference section explains the constraints available for LegUp HLS.

The main constraints available from the LegUp IDE are:

A few debugging constraints are available from the LegUp IDE:

7.1. CLOCK_PERIOD

This is a widely used constraint that allows the user to set the target clock period for a design. The clock period is specified in nanoseconds.

It has a significant impact on scheduling: the scheduler will schedule operators into clock cycles using delay estimates for each operator, such that the specified clock period is honored. In other words, operators will be chained together combinationally to the extent allowed by the value of the CLOCK_PERIOD parameter.

LegUp has a default CLOCK_PERIOD value for each device family that is supported (see table in LegUp Constraints).

Category

HLS Constraints

Value Type

Integer represent a value in nanoseconds

Valid Values

Integer

Default Value

Depends on the target device

Dependencies

Applicable Flows

All devices and flows

Test Status

Actively in-use

Examples

set_parameter CLOCK_PERIOD 15

7.2. set_custom_top_level_module

This Tcl command specifies the top-level C/C++ function. The top-level function and all of its descendant functions will be compiled to hardware. The top-level function can also be specified using a pragma (see Set Custom Top-Level Function), but it cannot be specified using both the Tcl command and the pragma.

Category

HLS Constraints

Value Type

string

Dependencies

NONE

Applicable Flows

All devices and flows

Test Status

Actively in-use

Examples

set_custom_top_level_module "foo"

7.3. set_custom_test_bench_module

This TCL command is to specify the name of the user-provided testbench module to be using for RTL simulation. The testbench file must also be specified with set_custom_test_bench_file.

Category

Simulation

Value Type

String

Dependencies

set_custom_test_bench_file user_tb.v

Applicable Flows

All devices and flows

Test Status

Actively in-use

Examples

set_custom_test_bench_module "user_tb"

7.4. set_custom_test_bench_file

This TCL command is to specify the user-provided custom testbench file that defines the custom testbench module, which is set via set_custom_test_bench_module. This is not needed for SW/HW co-simulation.

Category

Simulation

Value Type

String

Dependencies

set_custom_test_bench_module "user_tb"

Applicable Flows

All devices and flows

Test Status

Actively in-use

Examples

set_custom_test_bench_file user_tb.v

7.5. set_synthesis_top_module

This TCL command specifies the name of the Verilog module that will be set as the top-level module when creating a Libero project for synthesis, place and route. By default, the top-level function (see Specifying the Top-level Function) is set as the top-level module for the Libero project, however user may want to provide wrapper HDL module that instantiates the LegUp-generate top-level module. In this case, this Tcl command can be used to give the name of the wrapper module.

Category

Libero

Value Type

string

Dependencies

NONE

Applicable Flows

All devices and flows

Test Status

Actively in-use

Examples

set_synthesis_top_module "wrapper_top"

7.6. set_resource_constraint

This Tcl command constrains the resource allocated by LegUp. For instance, to only have a single divider in the entire circuit, user can specify: set_resource_constraint divide 1. This makes LegUp instantiate a maximum of 1 divider in the circuit, and if there are multiple division operations required, they will share the same divider.

Note: A constraint on “divide” will apply to:
  • signed_divide_8
  • signed_divide_16
  • signed_divide_32
  • signed_divide_64
  • unsigned_divide_8
  • unsigned_divide_16
  • unsigned_divide_32
  • unsigned_divide_64

It can also be used to constrain the number of memory ports. To make all memories single-ported: set_resource_constraint memory_port 1 For memory ports, only 1 and 2 are valid values, as FPGA RAMs have up to 2 ports.

This Tcl command should only be used by advanced LegUp users.

Category

HLS Constraints

Value Type

set_resource_constraint <operation> <constraint> <operation> is a string <constraint> is an integer

Valid Values

See Default and Examples Note: operator name should match the device family operation database file: boards/PolarFire/PolarFire.tcl

Default Values

memory_port 2
divide 1
modulus 1
multiply 2
altfp_add 1
altfp_subtract 1
altfp_multiply 1
altfp_divide 1
altfp 1

Location Where Default is Specified

examples/legup.tcl

Dependencies

None

Applicable Flows

All devices and flows

Test Status

Actively in-use

Examples

set_resource_constraint signed_divide_16 3

set_resource_constraint signed_divide 2

set_resource_constraint divide 1

7.7. set_operation_latency

This Tcl command sets the latency of a given operation. Latency refers to the number of clock cycles required to complete the computation; an operation with latency one requires one cycle, while zero-latency operations are completely combinational, meaning multiple such operations can be chained together in a single clock cycle. This command is used to schedule each type operation to take the specified number of cycles.

This Tcl command should only be used by advanced LegUp users.

Category

HLS Constraints

Value Type

set_operation_latency <operation> <constraint> <operation> is a string <constraint> is an integer

Valid Values

See Default and Examples Note: operator name should match the operation database file: boards/PolarFire/PolarFire.tcl or boards/set_operation_latency.tcl

Default Values

altfp_add 14
altfp_subtract 14
altfp_multiply 11
altfp_divide_32 33
altfp_divide_64 61
altfp_truncate_64 3
altfp_extend_32 2
altfp_fptosi 6
altfp_sitofp 6
signed_comp_o 1
signed_comp_u 1
reg 2
memory_port 2
local_memory_port 1
multiply 1

Location Where Default is Specified

examples/legup.tcl

Dependencies

None

Applicable Flows

All devices and flows

Test Status

Actively in-use

Examples

// set memory operations to take 3 cycles set_operation_latency memory_port 3

7.8. KEEP_SIGNALS_WITH_NO_FANOUT

If this parameter is enabled, all signals will be printed to the output Verilog file, even if they don’t drive any outputs.

Category

HLS Constraint

Value Type

Integer

Valid Values

0, 1

Default Value

unset (0)

Location Where Default is Specified

examples/legup.tcl

Dependencies

None

Applicable Flows

All devices and flows

Test Status

Actively in-use

Examples

set_parameter KEEP_SIGNALS_WITH_NO_FANOUT 1

7.9. VSIM_ASSERT

When set to 1, this constraint causes assertions to be inserted in the Verilog produced by LegUp. This is useful for debugging the circuit to see where invalid values (X’s) are being assigned.

Category

Simulation

Value Type

Integer

Valid Values

0, 1

Default Value

0

Location Where Default is Specified

examples/legup.tcl

Dependencies

None

Applicable Flows

All devices and flows

Test Status

Actively in-use

Examples

set_parameter VSIM_ASSERT 1