LegUp 9.1 Documentation

LegUp automatically compiles a C/C++ program into hardware described in Verilog HDL (Hardware Description Language). The generated hardware can be programmed onto an Microchip FPGA (Field-Programmable Gate Array). Hardware implemented on an FPGA can provide 2-10X performance and power benefits over the same computation running on regular processors.

The documentation is comprised of the following sections:

• Getting Started: Installation and a quick start guide
• User Guide: How to use LegUp to generate hardware
• Optimization Guide: How to optimize the generated hardware
• Hardware Architecture: Synthesized hardware architecture
• LegUp Pragmas Manual: Pragmas manual
• Constraints Manual: Constraints manual
• Frequently Asked Questions: Frequently asked questions

For example applications using LegUp please check out our github at:

• https://github.com/LegUpComputing/legup-examples

For support, please contact legup@microchip.com.

• 1. Getting Started
  • 1.1. Installation
    • 1.1.1. Windows
    • 1.1.2. Linux
    • 1.1.3. Libero and ModelSim
  • 1.2. Quick Start Tutorial
• 2. User Guide
  • 2.1. Introduction to High-Level Synthesis
    • 2.1.1. Instruction-level Parallelism
    • 2.1.2. Loop-level Parallelism
    • 2.1.3. Thread-level Parallelism
    • 2.1.4. Data Flow (Streaming) Parallelism
  • 2.2. LegUp Overview
  • 2.3. LegUp Pragmas
  • 2.4. LegUp Constraints
  • 2.5. Specifying the Top-level Function
  • 2.6. SW/HW Co-Simulation
  • 2.7. Loop Pipelining
  • 2.8. Multi-threading with Pthreads
  • 2.9. Supported Pthread APIs
  • 2.10. Data Flow Parallelism with Pthreads
    • 2.10.1. Further Throughput Enhancement with Loop Pipelining
  • 2.11. Function Pipelining
  • 2.12. Memory Partitioning
    • 2.12.1. An Access-Based Memory Partitioning Example
    • 2.12.2. A User-Specified Memory Partitioning Example
  • 2.13. LegUp C++ Library
    • 2.13.1. Streaming Library
    • 2.13.2. C++ Arbitrary Precision Data Types Library
    • 2.13.3. C++ Arbitrary Precision Integer Library
    • 2.13.4. C++ Arbitrary Precision Bit-level Operations
    • 2.13.5. C++ Arbitrary Precision Fixed Point Library
    • 2.13.6. Supported Operations in ap_[u]int, ap_[u]fixpt, and floating-point
    • 2.13.7. Image Processing Library
  • 2.14. LegUp C Library
    • 2.14.1. C Bit-Level Operation Library
    • 2.14.2. C Numerics Library (math.h in C / <cmath> in C++)
  • 2.15. Top-Level RTL Interface
    • 2.15.1. Module Control Interface
    • 2.15.2. Scalar Argument
    • 2.15.3. Pointer Argument and Shared Global Variable
    • 2.15.4. legup::FIFO Argument
  • 2.16. Specifying a Custom Test Bench
  • 2.17. Report Files
    • 2.17.1. LegUp Report
    • 2.17.2. Simulation and RTL Synthesis, Place & Route Report
  • 2.18. Instantiating LegUp IP Core in Libero SmartDesign
  • 2.19. LegUp Command Line Interface
• 3. Optimization Guide
  • 3.1. Loop Pipelining
  • 3.2. Loop Unrolling
  • 3.3. Function Pipelining
  • 3.4. Memory Partitioning
    • 3.4.1. Advanced Memory Partitioning
    • 3.4.2. Limitations and Workarounds
  • 3.5. Force Register
  • 3.6. Inferring a Shift Register
  • 3.7. Inferring a Line Buffer
  • 3.8. Inferring Streaming Hardware via Producer-Consumer Pattern with Pthreads
• 4. Hardware Architecture
  • 4.1. Circuit Topology
    • 4.1.1. Threaded Hardware Modules
  • 4.2. Memory Architecture
    • 4.2.1. Local Memory
    • 4.2.2. Shared-Local Memory
    • 4.2.3. Aliased Memory
    • 4.2.4. I/O Memory
    • 4.2.5. Memory Implementation
  • 4.3. Interfaces
• 5. Frequently Asked Questions
• 6. LegUp Pragmas Manual
  • 6.1. Set Custom Top-Level Function
  • 6.2. Pipeline Function
  • 6.3. Inline Function
  • 6.4. Noinline Function
  • 6.5. Flatten Function
  • 6.6. Replicate Function
  • 6.7. Pipeline Loop
  • 6.8. Unroll Loop
  • 6.9. Configure Scalar Argument Interface
  • 6.10. Configure Argument as Memory Interface
  • 6.11. Configure Global Variable as Memory Interface
  • 6.12. Configure Argument as Scalar Memory Interface
  • 6.13. Configure Global Variable as Scalar Memory Interface
  • 6.14. Configure Global as AXI4 Interface
  • 6.15. Partition Memory
  • 6.16. Partition Top-Level Interface
  • 6.17. Configure Arbiter Usage
• 7. Constraints Manual
  • 7.1. CLOCK_PERIOD
  • 7.2. set_custom_top_level_module
  • 7.3. set_custom_test_bench_module
  • 7.4. set_custom_test_bench_file
  • 7.5. set_synthesis_top_module
  • 7.6. set_resource_constraint
  • 7.7. set_operation_latency
  • 7.8. KEEP_SIGNALS_WITH_NO_FANOUT
  • 7.9. VSIM_ASSERT