LegUp 9.1 DocumentationΒΆ
LegUp automatically compiles a C/C++ program into hardware described in Verilog HDL (Hardware Description Language). The generated hardware can be programmed onto an Microchip FPGA (Field-Programmable Gate Array). Hardware implemented on an FPGA can provide 2-10X performance and power benefits over the same computation running on regular processors.
The documentation is comprised of the following sections:
- Getting Started: Installation and a quick start guide
- User Guide: How to use LegUp to generate hardware
- Optimization Guide: How to optimize the generated hardware
- Hardware Architecture: Synthesized hardware architecture
- LegUp Pragmas Manual: Pragmas manual
- Constraints Manual: Constraints manual
- Frequently Asked Questions: Frequently asked questions
For example applications using LegUp please check out our github at:
For support, please contact legup@microchip.com.
- 1. Getting Started
- 2. User Guide
- 2.1. Introduction to High-Level Synthesis
- 2.2. LegUp Overview
- 2.3. LegUp Pragmas
- 2.4. LegUp Constraints
- 2.5. Specifying the Top-level Function
- 2.6. SW/HW Co-Simulation
- 2.7. Loop Pipelining
- 2.8. Multi-threading with Pthreads
- 2.9. Supported Pthread APIs
- 2.10. Data Flow Parallelism with Pthreads
- 2.11. Function Pipelining
- 2.12. Memory Partitioning
- 2.13. LegUp C++ Library
- 2.13.1. Streaming Library
- 2.13.2. C++ Arbitrary Precision Data Types Library
- 2.13.3. C++ Arbitrary Precision Integer Library
- 2.13.4. C++ Arbitrary Precision Bit-level Operations
- 2.13.5. C++ Arbitrary Precision Fixed Point Library
- 2.13.6. Supported Operations in ap_[u]int, ap_[u]fixpt, and floating-point
- 2.13.7. Image Processing Library
- 2.14. LegUp C Library
- 2.15. Top-Level RTL Interface
- 2.16. Specifying a Custom Test Bench
- 2.17. Report Files
- 2.18. Instantiating LegUp IP Core in Libero SmartDesign
- 2.19. LegUp Command Line Interface
- 3. Optimization Guide
- 4. Hardware Architecture
- 5. Frequently Asked Questions
- 6. LegUp Pragmas Manual
- 6.1. Set Custom Top-Level Function
- 6.2. Pipeline Function
- 6.3. Inline Function
- 6.4. Noinline Function
- 6.5. Flatten Function
- 6.6. Replicate Function
- 6.7. Pipeline Loop
- 6.8. Unroll Loop
- 6.9. Configure Scalar Argument Interface
- 6.10. Configure Argument as Memory Interface
- 6.11. Configure Global Variable as Memory Interface
- 6.12. Configure Argument as Scalar Memory Interface
- 6.13. Configure Global Variable as Scalar Memory Interface
- 6.14. Configure Global as AXI4 Interface
- 6.15. Partition Memory
- 6.16. Partition Top-Level Interface
- 6.17. Configure Arbiter Usage
- 7. Constraints Manual